LUBIS EDA Revenue and Competitors

LUBIS EDA is helping customers to find simulation-resistant and corner-case bugs in high-risk silicon design or IP blocks.\n\nOur formal verification service enables you to:\n1)\tReach your silicon design verification goals faster \n2)\tUncover hard to find functional bugs in your design \n3)\tRequire less RTL simulation time\n4)\tStay within your budget and tape-out schedule\n5)\tAvoid re-spins and improve designer productivity\n\nWe functionally verify your RTL with formal techniques and iteratively communicate bugs we find. \nYou get short feedback cycles, reduce your time spent on RTL verification and higher-quality designs.\n\nWhat makes us special?\n\nWe work with an innovative formal verification methodology, resulting in an easy to use, high quality formal Verification IP. Instead of writing SVA properties by hand we established a property generation flow. During a verification service project, we build a propriatary model that enables us to generate VIP. The VIP can later be used in simulation and/or formal verification of your choice.