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Revathy Jeyaram Email
ASIC Verification Engineer . SmartDV Technologies
San Jose, CA
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SmartDV™ Technologies is the Proven and Trusted choice for design IP to verification solutions, including assertion-based and post-silicon validation IP, synthesizable transactors to accelerate verification on emulators and FPGA platforms, and memory models. \n\nSmartDV’s broad portfolio of design IP features cores that are used in hundreds of design projects throughout the global electronics industry across a spectrum of markets, including mobile, automotive, networking, communications, networking, SoC, storage, and memory. \n\nEngineering groups rely on SmartDV’s verification IP solutions developed by talented and experienced ASIC and SoC design and verification engineers. Here’s why:\n\n•\tProven track record with a large, repeat user base who trust SmartDV’s VIP solutions\n•\tLargest, most extensive up-to-date verification IP portfolio for a variety of chip design verification projects\n•\tProven and Trusted expertise that spans the chip design and verification space for exceptional support and service\n•\tSmartCompiler™, our proprietary automated compiler technology, enables the rapid development and deployment of first-to-market VIP to support new/updated industry standard protocols and also allows us to offer fast turnaround times on customization requests for design IP and VIP\n\nSmartDV is headquartered in Bengaluru, India, with U.S. headquarters in San Jose, California.SmartDV Technologies Address
San Jose, CA
United States